`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:57:22 07/26/2019 
// Design Name: 
// Module Name:    rst_led 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module rst_led(
   input wire  sck,
   output wire rst,
   output wire rst_lvds,
   output wire led,
   output reg  I_time_1ms_sync,
   input wire  I_vsync
    );
reg 	[27:0]	reset_count, time_cnt;   
wire            time_1ms;
reg             time_ms_r;
reg [13:0] lvds_rst_count;
reg rst_lvds_temp;


initial begin
    reset_count =26'd0;
    time_cnt   = 26'd0;
end

always@(posedge sck)
	if (reset_count[10] == 1'b0)
        	reset_count <= reset_count + 1'b1;        

assign rst = reset_count[10];             // active high reset pin
assign rst_lvds = rst_lvds_temp;

//LED计数
always @(posedge sck )
        time_cnt <= time_cnt + 1'b1;

assign	led = time_cnt[25];



        
//// 1ms
assign    time_1ms=time_cnt[16];


always    @(posedge sck)
begin
        time_ms_r<=time_1ms;        

end

always    @(posedge sck or negedge rst)
    if(rst==0)
            I_time_1ms_sync<=1'b0;
    else if(time_ms_r==1'b0 && time_1ms==1'b1) 
            I_time_1ms_sync<=1'b1;
    else 
            I_time_1ms_sync<=1'b0;


always@(posedge sck or negedge rst)
    if(rst==0)
        lvds_rst_count <=  12'd0;  
    else if (I_vsync) 
        lvds_rst_count <=  12'd0;
    else if (I_time_1ms_sync)
        lvds_rst_count <=  lvds_rst_count +1;


always@(posedge sck  or negedge rst )
   if(rst==0)
       rst_lvds_temp <= 1'b0;
   else if (lvds_rst_count[11:0] == 12'hffff)
       rst_lvds_temp <= 1'b0;
   else
       rst_lvds_temp <= 1'b1;


endmodule
